Power devices are widely used to carry large currents at high voltages. Since the early 1950's, developers of electronic power systems began to base their high power systems on semiconductor devices.
The power bipolar transistor was first developed in the early 1950's, and its technology has matured to a high degree, allowing the fabrication of devices with current handling capability of several hundred amperes and blocking voltages of 600 volts. However, despite the attractive power ratings achieved for bipolar transistors, there are several fundamental drawbacks in their operating characteristics. First, the bipolar transistor is a current-controlled device. A large base-drive current, typically one fifth to one tenth of the collector current, is required to maintain the power bipolar transistor in the on state. Even larger reverse base drive currents are necessary to obtain high speed turn-off. These characteristics make the base drive circuitry complex and expensive.
Bipolar transistors are also vulnerable to a second breakdown failure mode under the simultaneous application of a high current and high voltage to the device, as would commonly be required in inductive power circuits. It is also difficult to parallel bipolar power devices because the forward voltage drop in bipolar transistors decreases with increasing temperature. This decrease in forward voltage drop promotes diversion of the current to a single device which can lead to device failure.
The power Field Effect Transistor (FET) was developed to solve the performance limitations of power bipolar transistors. Power FETs are typically variants of the Insulated Gate FET (IGFET) or the Metal Insulator Semiconductor FET (MISFET). These device types are commonly referred to as Metal Oxide Semiconductor Field Effect Transistors (MOSFET) because they include a conducting gate electrode, typically metal, that is separated from a semiconductor surface by an intervening insulator, typically silicon dioxide. Accordingly, all field effect transistors which use a conducting gate electrode separated from a semiconductor surface by an intervening insulator will be referred to herein as MOSFETs.
The power MOSFET applies a control signal to the metal gate electrode that is separated from the semiconductor surface by an oxide. Accordingly, the control signal required is essentially a bias voltage with no significant steady-state gate current flow in either the on-state or the off-state. Even when switching between these states, the gate current is small because it only serves to charge and discharge the input gate capacitance. The high input impedance is a primary feature of the power MOSFET that greatly simplifies the gate drive circuitry and reduces the cost of the power electronics.
Moreover, because current conduction in the MOSFET occurs through majority carrier transport only, no delays are observed as a result of storage or recombination of minority carriers in power MOSFETs during turn off. Their switching speed is therefore orders of magnitude faster than that of bipolar transistors. Power MOSFETs also possess an excellent safe operating area. That is, they can withstand the simultaneous application of high current and voltage for a short duration without undergoing destructive failure due to second breakdown. Power MOSFETs can also easily be paralleled, because the forward voltage drop of power MOSFETs increases with increasing temperature. This feature promotes an even current distribution in parallel devices.
In view of the above desirable characteristics, many variations of power MOSFETs have been designed for power devices. Two of the most popular types are the double-diffused MOS (DMOS) device and an ultra-low on-resistance MOS device (UMOS). Both of these devices are vertical devices, in which the source is located on one face of a semiconductor substrate and the drain is located at the opposite face of the semiconductor substrate, so that carrier movement is transverse to the faces of the semiconductor substrate.
The DMOS structure, and its operation and fabrication are described in the textbook entitled Modern Power Devices, authored by the present inventor, the disclosure of which is hereby incorporated herein by reference. Chapter 6 of this textbook describes power MOSFETs at pages 263-343. FIG. 1 herein is a reproduction of FIG. 6.1(a) from the above cited textbook, and illustrates a cross-sectional view of a basic DMOS structure. As shown, the DMOS structure is fabricated using planar diffusion technology, with a refractory gate such as polycrystalline silicon (polysilicon). The p-base region and the n+ source region are typically diffused through a common window defined by the edge of the polysilicon gate. The p-base region is driven in deeper than the n+ source. The difference in the lateral diffusion between the p-base and n+ source regions defines the surface channel region. The p-n junction between the p-base region and the n-drift region provides forward blocking capability to carrier current from drain to source.
In the power DMOS, a conductive path is formed, extending between the n+ source region and the n-drift region. This can be accomplished by applying a positive gate bias to the gate electrode. The gate bias modulates the conductivity of the channel region by the strong electric field created normal to the semiconductor surface through the oxide layer. The gate induced electric field attracts electrons to the surface of the p-base region under the gate. This field strength is sufficient to create a surface electron concentration that overcomes the p-base doping. The resulting surface electron layer in the channel provides a conductive path between the n+ source regions and the drift region. Application of a positive drain voltage results in current flow between drain and source through the n-drift region and the channel.
To switch the power DMOS to the off-state, the gate bias voltage is reduced to zero by externally short circuiting the gate electrode to the source electrode. In order to insure that parasitic bipolar transistor operation is kept inactive during operation of the power DMOS, the p-base region is short circuited to the n+ emitter region by the source metallization shown in FIG. 1.
The UMOS device, also referred to as a "Trench DMOS" device, is described in publications entitled An UItra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process, by Ueda et al., IEEE Transactions on Electron Devices, Vol. ED34, No. 4, April, 1987, pp. 926-930; Numerical and Experimental Comparison of 60V Vertical Double-Diffused MOSFETS and MOSFETS with a Trench-Gate Structure by Chang, Solid State Electronics, Vol. 32, No. 3, pp. 247-251, 1989; and Trench DMOS Transistor Technology for High-Current (100A Range) Switching by Buluce et al., Solid State Electronics, Vol. 34, No. 5, pp. 493-507, 1991. The UMOS is a rectangular (U-shaped) groove MOSFET with a high packing density and a reduced channel resistance. The device is fabricated by diffusing p-body and n+ source regions into an n-epitaxial drift region of an n+ wafer. Reactive ion etching is used to form rectangular grooves or trenches in the substrate, followed by a gate oxidation. A first polysilicon layer is grown and slightly oxidized and a second polysilicon layer is deposited for groove filling. In order to form the gate, the first polysilicon layer is etched off and then the device is metallized. FIG. 2 herein is a reproduction of a portion of FIG. 1 of the above identified Ueda et al. publication illustrating an embodiment of the UMOS structure.
The above description of power MOSFETs has assumed that the junctions are semi-infinite. However, for practical devices it is necessary to consider edge effects to obtain a realistic design. The edge termination limits the breakdown voltage of practical devices to below the theoretical limits set by semi-infinite junction analysis. If the junction is poorly terminated, its breakdown voltage can be as low as 10-20% of the theoretical case. This severe degradation in breakdown voltage can seriously compromise the device design and lead to reduced current ratings as well.
Accordingly, much effort has been focused on the proper termination of the device region of power MOSFETs. It has been found that the diffusion process through a mask layer creates cylindrical junctions at the mask edges and spherical junctions at the sharp corners of the mask. These curvatures result in severe reduction in the breakdown voltage as a result of electric field crowding.
The art has solved the junction termination problem by providing a specially designed termination region around the periphery of the device. One approach for solving the termination problem uses "floating field rings". Floating field rings are formed of diffused regions that are isolated from the main junction but located close to it. These regions can assume a potential intermediate to that of either side of the junction. Their potential is established by the depletion layer extending from the main junction. Floating field rings are usually fabricated simultaneously with the main junction, because this can be achieved by creating an extra diffusion window in the mask that surrounds the main junction.
A detailed discussion of the design and fabrication of floating field rings and the manner in which they solve the breakdown voltage problem may be found in Section 3.6 of the above cited textbook by the present inventor, pages 79-100. A properly designed floating field ring can result in nearly a two-fold increase in the device's breakdown voltage. Multiple field rings can result in higher increases. FIG. 3 illustrates a silicon power UMOSFET structure including two diffused floating field rings in the termination region. The diffused floating field rings are typically fabricated by patterning the p-base diffusion at the device edges to form a planar termination to obtain high breakdown voltages.
Another approach for solving the termination problem uses "field plates". The field plate is typically a metal or other conductor ring at the edge of the planar junction. By altering the potential on the field plate, the depletion layer shape can be adjusted. The field plate is typically created by extending the junction metallization over the oxide. The presence of the field plate at the diffusion region potential forces the depletion layer to extend at the surface beyond the edge of the field plate. This reduces the depletion layer curvature and reduces the electric field. A detailed discussion of the design and fabrication of field plates and the manner in which they solve the breakdown voltage problem may be found in Section 3.6.7 of the above cited textbook by the inventor pp. 116-119. Typically, a field plate is used in conjunction with one or more floating field rings to achieve high breakdown voltage.
Almost all power MOSFETs being marketed today are fabricated in monocrystalline silicon. However, as is known to those skilled in the art, crystalline silicon carbide is particularly well suited for use in semiconductor devices, and in particular, for power semiconductor devices. Silicon carbide has a wide bandgap, a high melting point, a low dielectric constant, a high breakdown field strength, a high thermal conductivity and a high saturated electron drift velocity compared to silicon. These characteristics would allow silicon carbide power devices to operate at higher temperatures, higher power levels and with lower specific on resistance than conventional silicon based power devices.
A power MOSFET such as the above described DMOSFET or UMOSFET can be readily translated into silicon carbide using known manufacturing techniques. However, the formation of the floating field rings in the termination region would require very high temperature diffusions for very long time periods because the diffusion coefficient for dopants is much smaller in silicon carbide than in silicon. The use of these high temperatures would require specialized equipment that would increase processing costs. Moreover, the long diffusion times would add to the process cycle time, and adversely impact manufacturing volume and cost.